Embodiments of the present invention relate to maintaining an age order of entries in a processor, and more specifically, to maintaining an age management matrix including age and validity information of entries.
Within a microprocessor, it is often necessary to track age information about processor instructions or instruction addresses using entries in a queue-like structure. One such queue-like structure is a speculatively updated branch predictor which tracks multiple occurrences of process branches in a processor pipeline using speculatively updated branch prediction states prior to completion of the occurrences. Similar structures include issue queues for determining which instructions to issue in an out-of-order design, and fetch queues for determining which instruction addresses or data operand addresses to fetch from a cache or search for in a branch predictor. When attempting to predict a direction (taken vs. not-taken) of a most recent occurrence of a branch, it is necessary to select information from a youngest entry in the speculatively updated structure corresponding to that branch. Age management information entered into the structure should be maintained when entries are added and invalidated. Maintaining age management information is particularly challenging when there can be multiple additions and invalidations per cycle and when invalidations can occur in any order. Current structures employ time-consuming and resource-consuming methods for maintaining and tracking age entries. More efficient methods are needed for managing age ordering information incorporating both age and validity for timing-critical applications.